Frame Checking Sequence

Description

The Frame Checking Sequence is a fundamental error detection mechanism employed across multiple layers and interfaces in 3GPP systems, most notably at the physical layer and within data link layer protocols. It is a calculated value, derived from the bits of a transmitted frame (header and payload), which is appended to the frame before transmission. Common algorithms for generating the FCS include Cyclic Redundancy Check (CRC), with specific polynomials defined for different channels and protocols. Upon reception, the receiving entity independently recalculates the FCS based on the received bits and compares it to the received FCS value. If they match, the frame is considered error-free and is accepted for further processing. If they do not match, the frame is discarded, triggering error handling procedures such as a request for retransmission (in acknowledged mode) or being counted as a lost frame.

In the context of 3GPP radio access, FCS is integral to transport channels and physical layer processing. For example, in UMTS and LTE, a CRC is attached to each Transport Block (TB) before channel coding. The size of this CRC (e.g., 24 bits) is specified in the relevant physical layer specifications (25-series, 36-series). This allows the UE or base station to verify the integrity of the decoded transport block after forward error correction. A failed CRC indicates a decoding error, and this information is used for outer-loop power control and Hybrid Automatic Repeat Request (HARQ) processes. In HARQ, a failed CRC (indicated by a NACK) triggers a retransmission.

Beyond the physical layer, FCS is used in data link protocols like the Radio Link Control (RLC) protocol in Unacknowledged Mode (UM) and Acknowledged Mode (AM). Here, it protects RLC Protocol Data Units (PDUs). In the Packet Data Convergence Protocol (PDCP), an integrity checksum (which functions similarly to an FCS) is used for control plane signaling messages to protect against malicious tampering. Furthermore, for circuit-switched data services, protocols like V.42 error correction (referenced in TS 27.010) use FCS for reliable modem communication. The implementation details—the polynomial, initial value, and calculation scope—are meticulously defined in each specification to ensure interoperability between transmitters and receivers.

Purpose & Motivation

The primary purpose of the Frame Checking Sequence is to ensure the integrity of digital data transmitted over error-prone wireless and wired channels. Radio channels are inherently susceptible to noise, fading, and interference, which can flip bits during transmission. Without error detection, corrupted data would be processed by higher layers, leading to garbled voice, corrupted files, or incorrect signaling commands, severely degrading service quality and network stability. FCS provides a computationally efficient method to detect the vast majority of random bit errors.

Its creation and standardization were motivated by the need for reliable digital communication. Early digital systems required a way to automate error checking without human intervention. The FCS, particularly using CRC algorithms, offered a powerful trade-off: high error detection capability with relatively low overhead (a small number of extra bits per frame) and low computational complexity. It addresses the limitations of simple parity checks, which can only detect an odd number of bit errors. By enabling receivers to discard corrupted frames, FCS forms the basis for reliable data transfer protocols. It is the essential first step before any retransmission mechanism (like ARQ or HARQ) can function, as these mechanisms rely on a positive/negative acknowledgment based on the FCS check outcome.

Key Features

• Error detection for random and burst errors using CRC algorithms.
• Configurable CRC length (e.g., 8, 16, 24, 32 bits) based on required robustness.
• Integral part of Physical Layer Transport Block processing for HARQ.
• Used in RLC PDUs for integrity verification in Unacknowledged and Acknowledged Modes.
• Supports outer-loop power control by providing a Block Error Rate (BLER) measurement.
• Standardized polynomials and calculation procedures ensure interoperability.

Evolution Across Releases

Defining Specifications